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rev c, november 1999 november 2,1999 1 AN4003 pc power supply design with ka3511 sang-tae im 1. general description the ka3511 is a fixed-frequency improved-performance pulse-width modulation control circuit with complete housekeeping circuitry for use in the secondary side of smps (switched mode power supply). it contains various functions, which are precision voltage reference, over voltage protec- tion, under voltage protection, remote on/off control, power good signal generator and etc. ovp (over voltage protection) section it has ovp functions for +3.3v,+5v,+12v and pt outputs. the circuit is made up of a comparator with four detecting inputs and without hysteresis voltage. especially, pt (pin16) is prepared for an extra ovp input or another protection signal. uvp (under voltage protection) section it also has uvp functions for +3.3v, +5v, +12v outputs. the block is made up of a comparator with three detecting inputs and without hysteresis voltage. remote on/off section remote on/off section is used to control smps externally. if a high signal is supplied to the remote on/off input, pwm signal becomes a high state and all secondary outputs are grounded. the remote on/off signal is transferred with some on-delay and off-delay time of 8ms, 24ms respec- tively. precision reference section the reference voltage trimmed to 2% (4.9v< vref< 5.1v) pg (power good signal generator) section power good signal generator is to monitor the voltage level of power supply for safe operation of a microprocessor. ka3511 requires few external components to accomplish a complete housekeeping circuits for smps. the ka3511 is available in a 22-pin dual in-line package.
2 rev c, november 1999 ordering information features ? complete pwm control and house keeping circuitry few external components precision voltage reference trimmed to 2% dual output for push-pull operation each output tr for 200ma sink current variable duty cycle by dead time control soft start capability by using dead time control double pulse suppression logic over voltage protection for 3.3v / 5v / 12v under voltage protection for 3.3v / 5v / 12v one more external input for various protection (pt) remote on/off control function (ps-on) latch function controlled by remote and protection input power good signal generator with hysteresis 22-pin dual in-line package 2. block diagram device package operating temperature ka3511 22 dip -25 c ~ 85 c 7 8 oscillator 2 3 4 19 12 vref start up 1 9 delay controller 17 18 10 20 22 21 5 6 t rem 11 16 13 14 15 pt v12 v5 v3.3 pg rem (ps-on) e c2 c1 remote on/off 1.4v 1.25v vref 5v ovp comp 1.25v uvp comp gnd t uvp 2.2uf t pg 2.2uf comp3 1.8v 0.6v 1.8v 0.6v pg generator vref ichag comp2 comp1 1.25v 0.1v dead time controller pwm control q r s ck dq q 1.25v internal bias 5v det v cc vref dead time control e/a(+) e/a(-) v5 v12 comp c t r t 22-dip-400
3 rev c, november 1999 3. pin description pin no. name i/o function pin no. name i/o function 1 v cc i supply voltage 12 vref o precision reference vtg 2 comp o e/a output 13 v3.3 i ovp, uvp input for 3.3v 3 e/a(-) i e/a (-) input 14 v5 i ovp, uvp input for 5v 4 e/a(+) i e/a (+) input 15 v12 i ovp, uvp input for 12v 5 trem ? remote on/off delay 16 pt i extra protection input 6 rem i remote on/off input 17 t uvp ? uvp delay 7 rt ? oscillation freq. setting r 18 gnd ? signal ground 8 ct ? oscillation freq. setting c 19 dtc i deadtime control input 9 det i detect input 20 c2 o output 2 10 t pg ? pg delay 21 e ? power ground 11 pg o power good signal output 22 c1 o output 1 ka3511 v cc compe/a(-) ea(+) trem rem rt ct det tpg pg #1 #11 vref #12 v3.3 #22 v5 v12 pt tuvp gnd dtc c2 e c1
4 rev c, november 1999 pin no. name function 1 v cc supply voltage. operating range is 14v~30v. v cc =20v, ta=25 c at test. 2 comp error amplifier output. it is connected to non-inverting input of pulse width modulator comparator. 3 e/a(-) error amplifier inverting input. its reference voltage is always 1.25v. 4 e/a(+) error amplifier non-inverting input feedback voltage.this pin may be used to sense power supply output voltage. 5 trem remote on/off delay. ton/toff=8ms/24ms (typ.) with c=0.1f. its high/low threshold voltage is 1.8v/0.6v. 6 rem remote on/off input. it is ttl operation and its threshold voltage is 1.4v. voltage at this pin can reach normal 4.6v, with absolutely maximum voltage, 5.25v. if rem = ?low?, pwm = ?low?. that means the main smps is operational. when rem = ?high?, then pwm = ?high? and the main smps is turned-off. 7 rt oscillation frequency setting r. (test condition r t =10k ? ) 8 ct oscillation frequency setting c. (test condition c t =0.01f) 9 det under-voltage detect pin. its threshold voltage is 1.25v typ. 10 t pg pg delay. td=250ms (typ) with c pg =2.2f. the high/low threshold voltage are 1.8v/0.6v and the voltage of pin10 is clamped at 2.9v for noise margin. 11 pg power good output signal. pg = ?high? means that the power is ?good? for operation and pg = ?low? means ?power fail?. 12 vref precision voltage reference trimmed to 2%. (typical value = 5.03v) 13 v3.3 over voltage protection for output 3.3v. (typical value = 4.1v) 14 v5 over voltage protection for output 5v. (typical value = 6.2v) 15 v12 over voltage protection for output 12v. (typical value = 14.2v) 16 pt this is prepared for an extra ovp input or another protection signal. (typical value = 1.25v) 17 t uvp timing pin for under voltage protection blank-out time. its threshold voltage is 1.8v and clamped at 2.9v after full charging. target of delay time is 250ms and it is realized through external (c=2.2f). 18 gnd signal ground. 19 dtc deadtime control input. the dead-time control comparator has an effective 120mv input offset which limits the minimum output dead time. dead time may be imposed on the output by setting the dead time control input to a fixed voltage, ranging between 0v to 3.3v. 20 c2 output drive pin for push-pull operation. 21 e power ground. 22 c1 output drive pin for push-pull operation.
5 rev c, november 1999 4. absolute maximum ratings temperature characteristics characteristic symbol value unit supply voltage v cc 40 v collector output voltage v c1 , v c2 40 v collector output current i c1 , i c2 200 ma power dissipation p d 1 w operating temperature t opr -25 to 85 c storage temperature t stg -65 to 150 c characteristic symbol value unit min. typ. max. temperature coefficient of vref (-25 c< ta< 85c) ? vref/ ? t ? 0.01 ? %/c
6 rev c, november 1999 5. electrical characteristics (v cc =20v, t a =25c) characteristic symbol test condition value unit min. typ. max. reference section reference output voltage vref iref=1ma 4.9 5 5.1 v line regulation ? vref. line 14v< v cc < 30v ? 2.0 25 mv load regulation ? vref. load 1ma< iref< 10ma ? 1.0 15 mv temperature coefficient of vref (1) ? vref/ ? t -25c< ta< 85c ? 0.01 ? %/c short-circuit output current i sc vref=0 15 35 75 ma oscillator section oscillation frequency fosc c t =0.01f, r t =12k ? 10 ? khz frequency change with temperature (1) fosc/t c t =0.01f, r t =12k ? 2 ? % dead time control section input bias current i b(dt) ? -2.0 -10 a maximum duty voltage dc max pin19 (dtc)=0v 45 48 50 % input threshold voltage v th(dt) zero duty cycle ? 3.0 3.3 v max. duty cycle 0 ? ? error amp section inverting reference voltage vref(ea) 1.20 1.25 1.30 % input bias current i b(ea) v comp =2.5v ? -0.1 -1.0 a open-loop voltage gain (1) g vo 0.5v< v comp < 3.5v 70 95 ? db unit-gain bandwidth (1) bw ? 650 ? khz output sink current i sink v comp =0.7v 0.3 0.9 ? ma output source current i source v comp =3.5v -2.0 -4.0 ? ma pwm comparator section input threshold voltage v th(pwm) zero duty cycle ? 4 4.5 v output section output saturation voltage v ce(sat) i c =200ma ? 1.1 1.3 v collector off-state current i c(off) v cc =v c =30v, v e =0v ? 2 100 a rising time t r ? 100 200 ns falling time t f ? 50 200 ns protection section over voltage protection for 3.3v v ovp1 3.8 4.1 4.3 v
7 rev c, november 1999 5. electrical characteristics (continued) notes: 1. these parameters, although guaranteed over their recommended operating conditions are not 100% tested in production. 2. rem on delay time (pin6 rem: ?l? ?h?), rem off delay time (pin6 rem: ?h? ?l?) characteristic symbol test condition value unit min. typ. max. over voltage protection for 5v v ovp2 ? 5.8 6.2 6.6 v over voltage protection for 12v v ovp3 ? 13.5 14.2 15.0 v input threshold voltage for pt v pt ? 1.20 1.25 1.30 under voltage protection for 3.3v v uvp1 ? 2.1 2.3 2.5 v under voltage protection for 5v v uvp2 ? 3.7 4.0 4.3 v under voltage protection for 12v v uvp3 ? 9.2 10 10.8 v charging current for uvp delay i chg.uvp c=2.2f, v th =1.8v -10 -15 -23 ua uvp delay time t d.uvp c=2.2f 100 260 500 ms remote on/off section rem on input voltage v remh i rem = -200a 2.0 ? ? v rem off input voltage v reml ? ? ? 0.8 v rem off input bias voltage i reml v rem =0.4v ? ? -1.6 ma rem on open voltage v rem(open) ? 2.0 ? 5.25 v rem on delay time ton c=0.1f 4 8 14 ms rem off delay time toff c=0.1f 16 24 34 ms remote on/off section (2) detecting input voltage v in(det) ? 1.20 1.25 1.30 v detecting v5 voltage v 5(det) ? 4.1 4.3 4.5 v hysteresis voltage 1 hy1 comp1, 2 10 40 80 mv hysteresis voltage 2 hy2 comp3 0.6 1.2 ? v pg output load resistor r pg ? 0.5 1 2 k ? charging current for pg delay i chg.pg c=2.2f, v th =1.8v -10 -15 -23 ua pg delay time t d.pg c=2.2f 100 260 500 ms pg output saturation voltage v sat(pg) i pg =10ma ? 0.4 0.2 v total device standby supply current i cc ?? 10 20 ma
8 rev c, november 1999 6. block description & application informations 6.1 oscillator block figure 1. oscillator r t , c t the ka3511 is a fixed-frequency pulse width modulation control circuit. an internal-linear sawtooth oscillator is frequency-programmable by two external components, r t and c t . the oscillator fre- quency is determined by figure 2. oscillator frequency vs. timing resistance 6.2 pwm control block output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor c t to either of two control signals. the nor gates, which drive output transistors q1 and q2, are enabled only when the flip-flop clock-input line is in its low state. this happens only during that portion of time when the sawtooth voltage is greater than the control signals. therefore, an increase in control-signal amplitude causes a corresponding linear decrease of output pulse width. (refer to the timing diagram shown in figure 4) vref v cc c t r t 12 1 12 12 fosc 1.1 r t c t -------------------- - = 300k 2k 5k 10k 20k 50k 100k 200k 500k 1m 100k 10k 1k 100 30 1k i o - oscillator frequency r t . timing resistance( ? ) vcc=15v 1.0 f 0.1 f ct=0.01 f 0.001 f
9 rev c, november 1999 figure 3. pwm control block the control signals are external inputs that can be fed into the dead-time control, the error amplifier inputs, or the feedback input. the dead-time control comparator has an effective 120mv input off- set which limits the minimum output dead time. dead time may be imposed on the output by set- ting the dead time control input to a fixed voltage, ranging between 0v to 3.3v. the pulse width modulator comparator provides a means for the error amplifier to adjust the output pulse width from the maximum percent on-time, established by the dead time control input, down to zero, as the voltage at the feedback pin varies from 0.5v to 3.5v. the error amplifier may be used to sense power-supply output voltage, and its output is connect to noninverting input of the pulse width modulator comparator. with this configuration, the amplifier that demands minimum output on time, dominates control of the loop. when capacitor c t is discharged, a positive pulse is generated on the output of the dead time comparator, which clocks the pulse-steering flip-flop and inhibits the output transistors, q1 and q2. the pulse-steering flip-flop directs the modulated pulses to each of the two output transistors always for push-pull operation. the output frequency is equal to half that of the oscillator. the ka3511 has an internal 5.0v reference capable of sourcing up to 10ma of load current for external bias circuits. the reference has an internal accuracy of 2% with typical thermal drift of less than 50mv over an operating temperature range of -25c to 85c oscillator r t c t 7 8 2 4 3 ck dq q comp pwm control 1.25v q1 q2 output drive 0.12v dead time controller
10 rev c, november 1999 figure 4. operating waveform 6.3 deadtime control for soft-start figure 5. soft-start circuit deadtime control for soft-start makes a power supply output rising time (typ. 15ms) to reduce out- put ringing voltage for 3.3v, 5v, and 12v. if output rising time is too fast, output ringing voltage reaches ovp level. you can make a soft start function by add external components r1, r2 and c1 (refer to figure 5). at first the main power is turned-on, the deadtime control voltage keeps high state ( = 3v), and then go to the low voltage( = 105mv) that devided by r1, r2. feedback dead-time control ct ck q q output q1 output q2 19 12 3ma vref r1 47k r2 1k dtc remote on/off + c1 22uf v dtc low r2 r1 r2 + --------------------- - vref(5v) = 104.9mv =
11 rev c, november 1999 so output duty ratio will change from the minimum duty ratio to the maximum duty ratio. also, if the remote voltage is high, the deadtime control voltage will keep 3v (=3ma xr2 (1k ? )) by the internal 3ma current source for soft start. therefore, when the remote voltage is low, the dead- time control voltage will be changed from 3v to almost ground potential. and its soft start time dependent on external capacitor c1. 6.4 output voltage regulation figure 6. output regulation circuit +5v/+12v output voltages are determined by resistor ratio of r1,r2,r3 and r4. the resistor value can be changed by set condition and requirements. r5, c1 are the compensation circuit for stability. if output voltage (+5v or +12v) is increase, duty ratio of main power switch will be reduced by pwm control comparator signal and error amplifier output. therefore the output voltage will be reduced. on the contrary, if output voltage (+5v or +12v) is reduce, duty ratio of main power switch will be increased by pwm control comparator signal and error amplifier output. therefore the output volt- age will be increased. so the output voltage of power supply will be regulated. 2 4 3 +5v +12v comp e/a(-) e/a(+) r5 1k ? r2 33k ? r1 11k ? r3 2k ? r4 1k ? c1 103 vref pwm control comparator 1.25v err-amp
12 rev c, november 1999 6.5 ovp block ovp function is simply realized by connecting pin13, pin14, pin15 to each secondary output. r1, 2, 3, 4, 5, 6 are internal resistors of the ic. each ovp level is determined by resistor ratio and the typical values are 4.1v/6.2v/14.2v. ovp detecting voltage for +3.3v ovp detecting voltage for +5v ovp detecting voltage for +12v especially, pin16 (pt) is prepared for extra ovp input or another protection signal. that is, if you want over voltage protection of extra output voltage, then you can make a function with two exter- nal resistors. ovp detecting voltage for pt in the case of ovp, system designer should know a fact that the main power can be dropped after a little time because of system delay, even if pwm is triggered by ovp. so when the ovp level is tested with a set, you should check the secondary outputs (+3.3v/+5v/ +12v) and pg (pin11) simultaneously. you can know the each ovp level as checking each output voltage in just time that pg (pin11) is triggered from high to low. vref=5v 13 14 15 16 r101 r102 pt r1 r3 r5 3.3v 5v 12v r2 r4 r6 1.25v d c b a ovp comp set of r/s latch r102, r102 : external components vo v ovp 1 +3.3v () r 1 r 2 + r 2 -------------------- v a r 1 r 2 + r 2 -------------------- vref 4.1v == = v ovp 2 +5v () r 3 r 4 + r 4 -------------------- v b r 3 r 4 + r 4 -------------------- vref 6.2v == = v ovp 3 +12v () r 5 r 6 + r 6 -------------------- v c r 5 r 6 + r 6 -------------------- vref 14.2v == = v pt r 101 r 102 + r 102 ------------------------------- v d r 101 r 102 + r 102 ------------------------------- vref ==
13 rev c, november 1999 6.6 uvp block the ka3511 has uvp functions for +3.3v, +5v, +12v outputs. the block is made up of three input comparators. each uvp level is determined by resistor ratio and the typical values are 2.3v/4v/ 10v. uvp detecting voltage for +3.3v uvp detecting voltage for +5v uvp detecting voltage for +12v 13 14 15 vref=5v set of r/s latch r1 r3 r5 r2 r2 r6 1.25v a b c uvp comp 3.3v 5v 12v v uvp 1 +3.3v () r 1 r 2 + r 2 -------------------- v a r 1 r 2 + r 2 -------------------- vref 2.3v == = v uvp 2 +5v () r 1 r 2 + r 2 -------------------- v a r 1 r 2 + r 2 -------------------- vref 4v == = v uvp 3 +12v () r 1 r 2 + r 2 -------------------- v a r 1 r 2 + r 2 -------------------- vref 10v == =
14 rev c, november 1999 6.7 remote on/off & delay block figure 9. remote on/off delay block remote on/off section is controlled by a microprocessor. if a high signal is supplied to the remote on/off input (pin6), the output of comp6 becomes high status. the output signal is transferred to on/off delay block and pg block. if no signal is supplied to pin6, pin6 maintains high status (=5v) for rpull. when remote on/off is high, it produces pwm (pin6) ?high? signal after on delay time (about 8ms) for stabilizing system. then, all outputs (+3.3v, +5v, +12v) are grounded. when remote on/off is changed to ?low?, it produces pwm ?low? signal after off delay time (about 24ms) for stabilizing the system. if rem is low, then pwm is low. that means the main smps is operational. when rem is high, pwm is high and the main smps is turned-off. on/off delay time can be calculated by following equation. (k1, k2: constant value gotten by test) in above equation, typical capacitor value is 0.1uf. if the capacitor is changed to larger value, it can cause malfunction in case of ac power on at remote high. because pwm maintains low sta- tus and main power turns on for on delay time. so you should use 0.1uf or smaller capacitor. 6 5 12 rpull 5v comp6 comp pg block remote on/off rem q1 q2 ion/ioff ion trem trem 0.1uf + 2.2v 0.6v 1.8v b c vref pwm rem ton toff ton k 1 ctrem ? von ion --------------------------------------- 0.95 0.1 f2v 23 a ----------------------------- - = 8.2msec = toff k 2 ctrem ? voff ioff --------------------------------------- 0.8 0.1 f2.1v 8 a ---------------------------------- - = 24msec =
15 rev c, november 1999 6.8 r/s flip flop (latch) block figure 10. r-s f/f block diagram there is a r-s f/f (latch) circuit for shutdown operation in the ka3511. r-s f/f (latch) is con- trolled by ovp, uvp, and some delayed remote on/off signal. if any output of ovp or uvp is high, set signal of r-s f/f is high status and it produces pwm ?high? and main power is turned off. when remote signal is high, its delayed output signal is sup- plied to reset port of r-s f/f and it produces set low. so output q is low status. at this time, pwm maintains high status by delayed remote high signal. after main power is turned-off by ovp/uvp and initialized by remote, if remote signal is changed to low, main power becomes operational. when you test ka3511, remote on/off signal should be toggled once for initializing. ovp+ set reset qn+1 qn+1 low low low qn qn low low high high high high high low high low high low high low high on/off delay s r q ovp uvp start-up nor nor r-s ff q delayed remote remote on/off r-s f/f (latch) pg block pg generator
16 rev c, november 1999 6.9 power good signal generator figure 11. pg signal generator block power good signal generator curcuits generate ?on & off? signal depending on the status of out- put voltage to prevent the malfunctions of following systems like microprocessor and etc. from unstable outputs at power on & off. at power on, it produces pg ?high? signal after some delay (about 250ms) for stabilizing outputs. at power off, it produces pg ?low? signal without delay by sensing the status of power source for protecting following systems. v cc detection point can be calculated by following equation. recom- mended values of r11, r12 are external components. comp3 creates pg ?low? without delay when +5v output falls to less than 4.3v to prevent some malfunction at transient status, thus it improves system stability. when remote on/off signal is high, it generates pg ?low? signal without delay. it means that pg becomes ?low? before main power is grounded. pg delay time (td) is determined by capacitor value, threshold voltage of comp3 and the charg- ing current and its equation is as following. 9 10 14 12 11 vref r11 60k r13 vref comp1 v cc r12 4.7k det r14 1.25v comp2 remote on/off cpg 2.2uf + tpg q2 comp3 q3 pg pg comp ichg r15 1k vref +5v 0.6v 1.8v v det 1.25v 1 r11 r12 ---------- - + ?? ?? = 17.2v = td ? v ichg ----------- - pg vth ichg ------------------------ - 2.2 f2v 18 a ----------------------------- - 250ms ==
17 rev c, november 1999 considering the lightning surge and noise, there are two types of protections. one is a few sec- onds delay between tpg and pg for safe operation and another is some noise margin of pin10. noise_margin_of_t pg = v10(max) ? vth(l) = 2.9v ? 0.6v = 2.3v 7. about test method you can verify the ka3511 with a smps set. but you should pay attention to the device damage problem by increasing v cc . you should remove the sub-board after +5vsb drops to 0v and v cc of ka3511 is grounded and then fan stops under the remote low. ? ovp function of +3.3v/+5v/+12v you can test ovp for +3.3v/+5v/+12v by shorting pin16 and pin17 to gnd. ? uvp function of +3.3v/+5v/+12v you can simply test uvp for +3.3v/+5v/+12v by shorting pin16 to gnd. ? ovp input threshold voltage for pt the test condition is remote ?low? and you increase the supply voltage of pin16 using a dc power supply. when the voltage is over 1.2 x v, main power supply will shutdown. so, you can measure the shutdown point of main power supply, and that will be a ovp input threshold volt- age for pt. ? remote on/off delay time you can measure the time difference of remote on/off and the main power supply output as toggling the remote on/off. ? pg delay time in ac power-on time, secondary outputs are turned on and then after some delay time pg out- put is triggered from low to high. you can measure the time difference of +5v and pg in turn-on time.
18 rev c, november 1999 8. house keeping circuit using the ka3511 requires few external components to accomplish a complete housekeeping cir- cuits for smps. 22 21 20 19 18 17 16 15 14 13 12 4 5 6 7 8 9 10 11 1 2 3 vcc comp e/a(-) e/a(+) rem rt ct det t pg pg t rem c1 e c2 dtc gnd t uvp pt v12 v5 v3.3 vref 2k ? (1w) 15k ? 0.01uf 12k ? 2.2uf 1uf 2.2uf 2k ? (1w) 11k ? 33k ? 1.8k ? 0.1uf 1k ? 0.01uf + + + pg micom 12v 5v standby supply v cc =20v + + 12v 5v 3v k a 3 5 1 1
19 rev c, november 1999 9. typical characteristics v cc -i cc bandgap reference voltage pin19(dead time control voltage)-duty cycle ovp for 3.3v ovp for 5v ovp for 12v temperature characteristic 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0.000 0 10 203040 supply voltage [v] 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.73 deadtime control voltage [v] 7 6 5 4 3 2 1 0 5.0 5.5 6.0 6.5 7.0 i cc [a] duty ratio [%] 31.1% 21.8% 12.8% v5 [v] 5.010 5.008 5.006 5.004 5.002 -40 -20 0 20 40 60 80 100 120 140 temp [ c] vref [v] v pg [v] 5 4 3 2 1 0 3.6 3.8 4.0 4.2 4.4 4.6 v3.3 [v] v pg [v] 5 4 3 2 1 0 14.0 14.2 14.4 14.6 14.8 15.0 v12 [v] v pg [v]
20 rev c, november 1999 ovp for pt uvp for 3.3v uvp for 5v uvp for 12v remote on charging current rem on/off vth 5 4 3 2 1 0 1.15 1.20 1.25 1.30 1.35 vpt [v] v pg [v] v pg [v] pin 13 (v3.3) voltage [v] 5 4 3 2 1 0 21 22 23 24 25 v pg [v] 5 4 3 2 1 0 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 pin 14 (v5) voltage [v] pin 15 (v12) voltage [v] 5 4 3 2 1 0 9.0 9.5 10.0 10.5 11.0 v pg [v] 5 4 3 2 1 0 012345 v pg [v] vrem [v] -0.000016 -0.000018 -0.000020 -0.000022 -0.000024 0 50 100 150 200 250 irem [a]
21 rev c, november 1999 remote on open voltage detecting v cc voltage (det) detecting v5 voltage charging current for pg short circuit current hysteresis voltage 2 5 4 3 2 1 0 012345 vrem [v] v pg [v] 5 4 3 2 1 0 1.0 1.1 1.2 1.3 1.4 1.5 -0.000005 -0.000010 -0.000015 -0.000020 0 20 40 60 80 100 120 140 160 i pg [v] 5 4 3 2 1 0 4.0 4.2 4.4 4.6 4.8 5.0 pin 14 (5v) voltage [v] v pg [v] -0.032 -0.033 -0.034 -0.035 0 100 200 300 400 iref [a] 5 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 2.5 v pg [v] pin 9 (det) voltage [v] pin 10 (t pg ) voltage [v]
22 rev c, november 1999 error amp sink current reference voltage 0.002 0.00 -0.002 -0.004 -0.006 -0.008 0 20 40 60 80 100 120 140 isink & isource [a] 5 4 3 2 1 0 010203040 vref [v] supply voltage [v]
23 rev c, november 1999 10. package dimension 1 11 12 22 9.14 0.20 10.16 0.400 2.54 0.100 0.360 0.008 0~15 0.25 +0.10 ? 0.05 0.010 +0.004 ? 0.002 3.40 0.30 0.134 0.012 3.81 0.20 0.150 0.008 27.49 0.20 1.082 0.008 27.90 1.098 max 5.08 0.200 0.51 0.020 max min 1.05 0.041 () 0.46 0.10 0.018 0.004 0.060 0.004 1.52 0.10 22-dip-400
24 rev c, november 1999 11. experimental result figure 12. rising time of +5vdc output voltage figure 13. pg signal delay time ch1 : ps-on ch2 : +5vdc output ch3 : pg signal ch1 : ps-on ch2 : +5vdc output ch3 : pg signal
25 rev c, november 1999 figure 14. power down warning figure 15. no load protection ch1 : ps-on ch2 : +5vdc output ch3 : pg signal ch1 : +3.3vdc output ch2 : +5vdc output ch3 : +12vdc output
26 rev c, november 1999 figure 16. vcc, +5vdc output vs. pg signal (high) figure 16. vcc, +5vdc output vs. pg signal (low) ch1 : vcc ch2 : +5vdc output ch3 : pg signal ch1 : vcc ch2 : +5vdc output ch3 : pg signal
27 rev c, november 1999 12. application circuit reference 1. power electronics by marvin j. fisher 2. principles of power electronics by kassakian author: sang-tae im: p-ic application team tel. 82-32-680-1275 fax. 82-32-680-1317 e-mail. sangtae.im@fairchildsemi.co.kr c6 22uf + 2.2uf + ic1 ar3511x vcc 1 c1 22 comp 2 e 21 e/a(-) 3 c2 20 dtc 19 e/a(+) 4 trem 5 gnd 18 rem 6 tuvp 17 rt 7 pt 16 ct 8 v12 15 det 9 v5 14 tpg 10 v3.3 13 pg 11 vref 12 ct 15k r5 70k r6 47k r4 1.2k r3 56k 100k 103 0.1uf + c16 + 2.2uf + 103 d19 d9 vr1 5v out 12v out power on out ref pg 3.3v out vcc c1 c2
trademarks acex? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast ? fastr? gto? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. tinylogic? uhc? vcx? isoplanar? microwire? pop? powertrench qfet? qs? quiet series? supersot?-3 supersot?-6 supersot?-8 ?

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